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【Technical class】S7 200 SMART high-speed counting introduction
In actual process control, high-speed pulse signals are often encountered, such as incremental encoders, some flow meters, etc. To correctly count and process these high-speed pulse signals, the high-speed counter function of PLC needs to be used. High-speed counters can count high-speed events that standard counters cannot control.
2 Number and performance of high-speed counters
• The compact model supports a total of four HSC devices (HSC0, HSC1, HSC2 and HSC3).
· SR and ST models (firmware version V2.3 and above) support a total of six HSC devices (HSC0, HSC1, HSC2, HSC3, HSC4 and HSC5).
3 Assignment and functions of high-speed counters
HSC0, HSC2, HSC4 and HSC5 support eight count modes (modes 0, 1, 3, 4, 6, 7, 9 and 10)
HSC1 and HSC3 only support one counting mode (mode 0)
High-speed counter input connections (clock, direction, and reset) must use the CPU's integrated input channels, input channels on signal boards or expansion modules cannot be used for high-speed counters
All high-speed counter inputs are connected to an internal input filter circuit. The default input filter setting of the S7-200SMART is 6.4 ms, which limits the maximum count rate to 78 Hz. To count at higher frequencies, the filter settings must be changed. See below:
Input points that have been used for high-speed counting cannot be used for other purposes. For example, all counting modes of HSC0 always use I0.0, so when HSC0 is used, I0.0 cannot be used for other purposes.
The following table shows the maximum input frequency that can be detected by the high-speed counter for various input filtering configurations:
5 High-speed counter addressing
The following takes the control word of HSC0 (high-speed counter 0) as an example to introduce the actual function of each bit of the special function register.
6 Programming of high-speed counters
To use a high-speed counter, a program must perform the following basic tasks:
①Define the counter and mode (execute HDEF instruction once for each counter)
②Set control byte in SM memory
③Set the current value (start value) in the SM memory
④Set the preset value (target value) in SM memory
⑤ Allocate and enable the corresponding interrupt routine
⑥Activate high-speed counter (execute HSC instruction)
HDEF, high-speed counter definition instruction. Defines the mode of the high-speed counter.
HSC, high-speed counter instruction. The high-speed counter is configured and controlled according to the state of the special memory bits of the high-speed counter.
While the above steps can be cumbersome and error-prone, the high-speed counter wizard can also be used to simplify the programming task. The process of wizard setting is the process of assigning addresses to control bytes.
After completing the wizard setting, a subprogram will be automatically generated, and the content of the subprogram is the creation of the basic tasks mentioned above.
1) In the menu bar, select Tools > Wizard > High Speed Counter
3) Define the name of the high-speed counter
4) Select mode
5) Define the counting direction and other characteristics of the high-speed counter. The settings here will affect the default value of the control byte in the special register.
6) Configuration interrupt
A high-speed counter can have up to 3 interrupt events, fill in the interrupt service routine name in the white box or use the default name.
The interrupt is generated when the current value is equal to the preset value. Through the wizard, the parameters of the high-speed counter, such as preset value and current value, can be reset in the interrupt service routine. One such process is called 'one step', and up to 10 steps can be set.
The relevant interrupt events in high-speed counting are as follows:
7) Complete the wizard
8) call subroutine
HSC_INIT is an initialization subroutine, and the high-speed counter can work normally after calling this subroutine once using SM0.1 or an edge-triggered instruction in the main program block.
The interrupt service routines and subroutines generated by the wizard are not locked and can be modified according to their own control needs.
7 Instruction introduction
8 Frequently Asked Questions
8.1 How to keep the current value of the high-speed counter after power off
The power-off data retention of the S7-200 SMART does not support the range setting of the high-speed counter, so the current value of the high-speed counter is reset to the value 0 every time the CPU is powered off. To keep the current value of the high-speed counter even after the CPU is powered off and restarted, it needs to be programmed. Ideas: First, in other cycles except the first scan cycle, the current value of the high-speed counter needs to be transferred to the V area register. Then, in the first cycle of power-on, the value stored in the V area register is transferred to the current value SMD of the high-speed counter to ensure that the high-speed counter starts counting with the value of the V area as the initial value, and the high-speed counter is initialized. Finally, the V area register is set as the power-off holding area at the power-off data holding place of the system block.
Taking high-speed counter 0 as an example, the programming is as follows:
8.2 How to reset the high-speed counter to 0?
Method 1: Select a high-speed counter with external reset mode. When the reset signal is valid, the high-speed counter is reset to 0.
Method 2: Reset the internal program, set the relevant bit of the update current value control byte of the high-speed counter to 1, and set 0
Assigned to special register SMD38, after executing HSC instruction, the high-speed counter is reset to 0.